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System Devicetree Specification

• 1. Introduction
  • 1.1. Purpose and Scope
  • 1.2. Relationship to the Devicetree Specification
  • 1.3. Summary of Extensions
  • 1.4. Usage Environments
  • 1.5. Definition of Terms
• 2. Hardware Description
  • 2.1. CPU Cluster Binding
    • 2.1.1. CPU Cluster Properties
    • 2.1.2. CPU Node Properties
    • 2.1.3. address-map Property
    • 2.1.4. #ranges-address-cells Property
    • 2.1.5. #ranges-size-cells Property
  • 2.2. Example CPU Clusters
    • 2.2.1. Single-core Arm Cortex-M3
    • 2.2.2. Dual-core Arm Cortex-R5
  • 2.3. Indirect Bus Binding
    • 2.3.1. Indirect Bus Properties
  • 2.4. The Default Cluster, /cpus
  • 2.5. Example System Devicetree Hardware Descriptions
    • 2.5.1. Simple example
    • 2.5.2. More complex example
• 3. Execution Domains
  • 3.1. Example
  • 3.2. Execution Domain Binding, v1
    • 3.2.1. cpus Property
    • 3.2.2. access Property
    • 3.2.3. memory Property
    • 3.2.4. sram Property
    • 3.2.5. os,type Property
    • 3.2.6. Implicit Flags Properties
  • 3.3. Default Execution Domain
  • 3.4. Per-Domain Reserved Memory and Chosen Nodes
• 4. Bus Firewalls (Under Discussion)
  • 4.1. Hardware Description
    • 4.1.1. Bus Firewall Controllers
    • 4.1.2. Device Protection
    • 4.1.3. Full Example
  • 4.2. Configuration
    • 4.2.1. firewallconf
    • 4.2.2. firewallconf-default
    • 4.2.3. Full Example
• 5. OpenAMP RemoteProc (Under Discussion)
  • 5.1. System Device Tree
    • 5.1.1. System Device Tree Example
    • 5.1.2. Device Tree Conversion and Example
• 6. Simplified YAML (Under Discussion)
  • 6.1. Basics
    • 6.1.1. Nodes, Properties, and Hierarchy
    • 6.1.2. Example
  • 6.2. Simplifications
    • 6.2.1. Strings
    • 6.2.2. reg and other address ranges
    • 6.2.3. #address_cells and #size_cells
    • 6.2.4. #interrupt_cells and others
    • 6.2.5. Phandles
    • 6.2.6. Boolean Properties
  • 6.3. Full Example
  • 6.4. Anchors, aliases and Merge Key Language-Independent Type
• 7. Domain Specific YAML Simplifications (Under Discussion)
  • 7.1. Hierarchy
  • 7.2. Access
  • 7.3. Memory and Sram
  • 7.4. Cpus
  • 7.5. Flags
  • 7.6. Implicit Flags Example
  • 7.7. Bus Firewalls
  • 7.8. Full Example
• 8. Appendix: Example System Devicetree
• 9. Bibliography